1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a fuse repair circuit for a semiconductor memory device.
2. Description of the Conventional Art
If there is a defective cell among numerous minute cells, a memory is not able to perform its function properly, thus being handled as an inferior memory. However, as the memory has been more integrated, there is high probability that defect is generated in a small amount of cells, but to regard a whole memory which has a little defect as the defective memory is not an effective way, which reduces the yield. Thus, generally a redundancy cell is provided in a semiconductor memory and when a cell has defect, the bad cell is repaired by using a reserved redundancy cell, for thereby increasing the yield. In such configuration, a fuse repair circuit is programmed with address information regarding a row redundancy and a column redundancy and then a bad cell is repaired by using the reserved redundancy cell when an inputted address (a column address or a row address) accords with the programmed address information. FIG. 1 illustrates a conventional fuse repair circuit of a semiconductor memory in a block diagram form. As shown therein, the conventional fuse repair circuit is provided with a cell array 10, a row fuse block 20 and a column fuse block 30, the row fuse block 20 and the column fuse block 30 driving a row redundancy 50 and a column redundancy 51, respectively, of the cell array 10. The row fuse block 20 outputs a matching signal MATR at a high level when receiving a row address RA identical to programmed row redundancy information, while the column fuse block 30 outputs a matching signal MATC at a high level when receiving a column address CA identical to programmed column redundancy information.
FIG. 2 shows the row fuse block 20 in more detail. More specifically, the row fuse block 20 includes a plurality of fuse units 101-104 for programming row redundancy information to be repaired and comparing the programmed row redundancy information with an inputted row address, and a NOR gate 105 for outputting the matching signal MATR for enabling the row redundancy 50 by NORing compare signals A-D from the fuse units 101-104. Here, the number of the fuse units 101-104 is varied by the number of bits of the row address RA. Further, each of the fuse units 101-104 includes PMOS transistors PM1, PM2 connected in parallel between a source voltage Vcc and a node P, a fuse F1 connected between the node P and a ground voltage Vss, an inverter INV1 connected between the node P and a gate of the PMOS transistor PM2, and an exclusive-OR gate EXOR comparing the row address with an output from the inverter INV1, wherein a precharge signal PRECH is inputted to a gate of the PMOS gate PM1. Here, a power-up signal is used for the precharge signal PRECH in the row block 20 and the power-up signal or a row address strobe (RAS)-system signal is used for the precharge signal PRECH in the column fuse block 30.
The column fuse block 30 has the same construction as the row fuse block 20. However, in the column fuse block 30, column redundancy information is programmed in a fuse F1 of the column fuse block 30, each fuse unit 101-104 compares an inputted column address CA with the programmed column redundancy information, and a NOR gate 105 outputs the matching signal MATR for enabling the column redundancy 51.
In such conventional fuse repair circuit, after fabricating a semiconductor memory, a user tests the memory cells for thereby judging whether or not the cells are in a good condition. Here, when there are many inferior cells, the user abolishes the fabricated memory, but if there is minority of defective cells, the user programs the redundancy information in the row fuse block 20 and the column fuse block 30, respectively, so that redundancy cells can be substituted for the defective cells. That is, the user programs the redundancy information by selectively cutting the fuses F1 in the fuse units 101-104 in accordance with a test result.
For instance, when a cell in an address `1000` is determined to be defective, the user programs redundancy information of `0111` in each of the fuse units 101-104 of the row fuse blocks 20 or the column fuse block 30 so that the defective cell can be repaired by a redundancy cell. Namely, `0111` is programmed on the basis of a potential of the node P thereof by not cutting the fuse F1 of the fuse unit 101, but cutting each fuse F1 of the other fuse units 102-104.
Next, when power is applied, the precharge signal PRECH becomes a high level and thereby the PMOS transistor PM1 of each of the fuse units 101-104 is turned on. When the PMOS transistor PM1 is turned on, each node P is precharged and thus the node P of the fuse unit 101 becomes a low level and all of the nodes P of the other fuse units 102-104 become a high level. Accordingly, the inverters INV1 of the fuse units 101-104 invert respectively the potential of the nodes P, thereby outputting signals of `1000` to the exclusive-OR gates EXOR.
Accordingly, the exclusive-OR gates EXOR of the fuse units 101-104 output the compare signals A-D at the low level when receiving the row address RA of `1000` and the NOR gate 105 NORs the compare signals A-D at the low level and thus outputs the matching signal MATR at the high level, for thereby driving the row redundancy 50. While, during a column address strobe (CAS) cycle, the exclusive-OR gates EXOR output the compare signals A-D when receiving the column address CA of `1000`, and the NOR gate 105 NORs the compares signals A-D at the low level and thus outputs the matching signal MATC at the high level, for thereby driving the column redundancy 51.
As described above, since the conventional fuse repair circuit drives the row redundancy and the column redundancy by the row fuse block and the column fuse block, respectively, the fuse repair circuit has a problem of increase in a chip size because the two fuse block which perform the same function are unnecessarily required to be used.